This application claims the priority benefit of Taiwan application serial no. 89123054, filed Nov. 2, 2000.
1. Field of Invention
The present invention relates to a method of manufacturing flash memory. More particularly, the present invention relates to a method of manufacturing the floating gate of a flash memory.
2. Description of Related Art
Non-volatile memory is now extensively used in many electronic devices such as data storage units. Nowadays, many types of non-volatile memories can even be programmed and erased by electrical means, for example, the electrical erasable programmable read-only-memories (EEPROMs). The programmability and erasability of data in a conventional EEPROM is achieved through the floating gate of a transistor. The floating gate facilitates writing, erasing and storage of data. However, EEPROMs has a slower accessing speed. Hence, a faster-operating EEPROM device known as flash memory has been developed.
In general, each flash memory cell has two gate structures, one is a floating gate while the other is a control gate. The floating gate is an electrode for holding electric charges. The control gate is an electrode that controls the writing and reading of data to and from the memory cell. In general, the control gate is connected to a word line and the floating gate is located above the control gate. The floating gate is typically disconnected from other circuitry, that means, the floating gate is in a xe2x80x98floating xe2x80x99 state. According to the position of the control gate, a flash memory cell can be divided into a stacked gate type and a detached gate type.
The channel of a conventional detached gate type of flash memory generally has two portions, a control gate channel and a floating gate channel. By controlling the two channels, on/off states of the memory cell are under control. The control gate of the detached gate flash memory covers only a portion of the floating gate. The control gate and the floating gate are coupled to each other through a coupling ratio (xcex1CF). In general, the coupling ratio between the control gate and the floating gate needs to be increased and alignment errors need to be prevented. This is because alignment errors can lead the active region not covered by the floating gate forming a conductive channel between the source and the drain terminal after the control gate is formed. Hence, a portion of the isolation region is normally covered by the floating gate to increase the coupling ratio and to ensure complete coverage of the active region by the floating gate.
FIGS. 1 through 7 are perspective views showing the progression of steps for producing the floating gate of a conventional flash memory. As shown in FIG. 1, a substrate 100 is provided. The substrate 100 has a shallow trench isolation (STI) structure 102. A gate oxide layer 104 is formed over the substrate 100. A doped polysilicon layer 106 is formed over the gate oxide layer 104 later serving as a floating gate. A silicon nitride layer is formed over the polysilicon layer 106. To obtain a floating gate with a width of about 3000 xc3x85, the silicon nitride layer 108 must have a thickness slightly greater than 3000 xc3x85. A patterned photoresist layer 110 is formed over the silicon nitride layer 108 so that positions of the floating gate are defined.
As shown in FIG. 2, the exposed silicon nitride layer 108 is removed to expose a portion of the polysilicon layer 106. The exposed polysilicon layer 106 is oxidized to form a floating gate oxide layer 112. Because oxidation of the polysilicon layer 106 near the sides of the silicon nitride layer 108 is constrained by the silicon nitride layer 108, a bird""s beak profile is formed near the edge of the floating gate oxide layer 112.
As shown in FIG. 3, another silicon nitride layer is formed over the silicon nitride layer 108 and the floating gate oxide layer 112. The newly deposited silicon nitride layer is etched back to expose the silicon nitride layer 108. Ultimately, spacers 114 are formed on the sidewalls of the silicon nitride layer 108 above the floating gate oxide layer 112. Due to the etching step, the spacers 114 cover only a portion of the floating gate oxide layer 112. The portion on each side still covered by the spacers 114 becomes the width of the floating gate. Thereafter, the floating gate oxide layer 112 not covered by the spacers 114 is removed to expose the polysilicon layer 106. Thus, the floating gate oxide layer 112 is cut into two separate portions.
As shown in FIG. 4, the silicon nitride layer 108 and the spacers 114 are removed until the polysilicon layer 106 and the floating gate oxide layer 112 underneath them are exposed. Another silicon nitride layer 116 is formed over the polysilicon layer 106 and the floating gate oxide layer 112. A patterned photoresist layer is formed over the silicon nitride layer 116. The silicon nitride layer 116 not covered by the photoresist layer is removed to turn the silicon nitride layer 116 into one having a shape shown in FIG. 4.
As shown in FIG. 5, yet another silicon nitride layer is formed over the silicon nitride layer 116 and the floating gate oxide layer 116. The newly deposited silicon nitride layer is etched back to expose the silicon nitride layer 116 and the floating gate oxide layer 112. Hence, spacers 118a are formed on the sidewalls of the silicon nitride layer 116 and spacers 118b are formed on the inner sidewalls of the floating gate oxide layer 112.
One major function of the second spacers 118a is to form a floating gate whose edges can cross over the shallow trench isolation, thereby preventing conduction between the source and the drain terminal. Meanwhile, separation between the floating gates will be reduced to smaller than the feature size due to the presence of the spacers 118a. Hence, a higher level of integration can be obtained.
Finally, as shown in FIGS. 6 and 7, the floating gate oxide layer 112 not covered by the spacers 118a and 118b is removed. The silicon nitride layer 116 and the spacers 118a, 118b are removed. The polysilicon layer 106 not covered by the floating gate oxide layer 112 is removed to expose the gate oxide layer 104. Thus, manufacturing steps necessary for producing the floating gate of a flash memory is complete.
The spacers 118a on the sidewalls of the silicon nitride layer 116 protect the underlying floating gate oxide layer 112 against reacting agents so that the edges of the ultimately formed floating gate cross over the shallow trench isolation 102. The crossing of the edges of the floating gate over the shallow trench isolation 102 not only increases the coupling ratio between the floating gate and the control gate, but also prevents alignment errors. Alignment errors can lead the active region not covered by he floating gate forming a conductive channel between the source and the drain terminal after the control gate is formed.
In general, the side edges of a conventional floating gate oxide layer will cross over the shallow trench isolation. Although such a structure has the advantage of preventing conduction between the source and the drain terminal, production steps are complicated and hence costly. Moreover, to obtain a floating gate having a width of 3000 xc3x85, the silicon nitride layer 108 must have a thickness slightly greater than 3000 xc3x85. Since the spacers 114 are formed on the sidewalls of the silicon nitride layer 108, thickness of the spacers 114 must also be greater than 3000 xc3x85. Such a thick layer of spacers 114 not only can cause particle contamination during deposition, but can also cause longer period to strip it off in a subsequent step.
Accordingly, one object of the present invention is to provide a method for manufacturing a floating gate that involves forming a buffer layer, a first spacer and a second spacer. The method is capable of avoiding the use of a thick first spacer.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for manufacturing the floating gate of a flash memory. First, a substrate is provided. A gate oxide layer, a polysilicon layer and a silicon nitride layer are sequentially formed over the substrate. Gate position is defined and then the silicon nitride layer above the gate position is removed. The exposed polysilicon layer is oxidized to from a floating gate oxide layer. A buffer layer is formed over the silicon nitride layer and the floating gate oxide layer. A first spacer is formed on the sidewall of the buffer layer. hereafter, a second spacer is formed. Using the second spacer as a mask, the exposed floating-gate oxide layer is removed. The buffer layer, the first spacer and the second spacer above the polysilicon layer and the floating gate oxide layer are removed. Finally, the polysilicon layer not covered by the floating gate oxide layer is removed to form a complete floating gate of a flash memory.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.